The present invention relates to a system for transmitting data to an auxiliary memory device connected to a microprocessor.
Data transmission between a microprocessor and an external auxiliary memory device is conventionally performed by using a common random access memory (to be referred to as a common RAM hereinafter). Such a conventional system is shown by a block diagram of FIG. 1. Reference numeral 1 denotes a microprocessor (to be referred to as an MPU hereinafter) of a main device; and 2, an auxiliary memory device. The auxiliary memory device 2 has a data transmission/reception common RAM 4, data bus transceivers 5 and 6, and a memory medium 9 such as a magnetic disk. Reference numerals 7 and 8 denote buses, respectively.
With the above arrangement, when data is transmitted or received,
(1) the MPU 1 in the main device writes command data in the common RAM 4,
(2) the MPU 3 in the auxiliary memory device reads command data from the common RAM 4,
(3) the MPU 3 writes an execution result in the common RAM 4, and
(4) the MPU 1 reads the execution result from the common RAM 4.
Among operations (1) to (4), operations (1) and (2) or operations (3) and (4) are often simultaneously performed. In this case, when the MPUs 1 and 3 simultaneously access the common RAM 4, one of the MPUs is halted while the other MPU is being operated according to the conventional system. For example, access from the MPU 1 is performed while the operation of the MPU 3 is halted. When the operation of the MPU 1 is completed, the operation of the MPU 3 is started.
When one MPU must read or write access the common RAM 4 at high speed, this MPU must exclusively use the common RAM.
For example, when the MPU 3 in the auxiliary memory device 2 exclusively uses the common RAM 4 for direct memory access transfer, the MPU 1 in the main device must wait for a long period of time when it accesses the common RAM 4. As a result, the MPU 1 cannot perform other operations. In order to allow access of the common RAM 4 by the MPU 1 even during this period, data transfer from the MPU 3 is delayed, resulting in inconvenience.